TDR Simulator
TRN553
Circuit Parameters
Source impedance Zs 50 Ω
Line Z0 50 Ω
Char. impedance — seen only by waves
Line delay TD 1.0 ns
Reflection arrives at t = 2·TD
Source voltage E 1.0 V
Rise time RT 0.15 ns
Resolution requires TD > ½RT
Load Impedance ZL
ZL ∞ Ω
Presets from lecture slides
Playback
Animation speed 1.0×
Termination Open Circuit Full reflection · in-phase · voltage doubles at load
VOLTAGE AT SOURCE PORT (V)
Vinitial
E · Z0 / (Zs + Z0)
Γload
(ZL − Z0) / (ZL + Z0)
Vreflected
Γ · Vinitial
Return Loss
−20 log10|Γ|
Reflection arrival
Round-trip = 2 · TD